STEVEN M. NOWICK


 
Office:
                Department of Computer Science
                Columbia University
                Room 508, Computer Science Building; Mail Code: 0401
                1214 Amsterdam Avenue
                New York, NY 10027

                Phone:  (212) 939-7056
                FAX:    (212) 666-0140

                E-mail:  nowick AT cs DOT columbia DOT edu
 


I am a Professor of Computer Science and Electrical Engineering, and was former chair of the Computer Engineering Program (2008-2013), at Columbia University.  I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976. My main research interests are:  the design and optimization of asynchronous and mixed-timing (i.e. mixed-clock, asynchronous/synchronous) digital circuits and systems; networks-on-chip (NoC's); low-latency interconnection networks for shared-memory multiprocessors; computer-aided design (CAD) tools; logic synthesis; fault tolerance and reliability; encoding techniques for low-power delay-insensitive communication; and ultra-low power digital systems.


Short Profile of My Research (PDF): (click here) 

Detailed Research Summary (PDF): (click here)  (covers my main research areas, recent papers, technology transfer, grants)


CV's:


Recent News...:


Research Slides:

Overview:

Networks-on-Chip:

High-Performance Pipelines:

Mixed-Timing Interfaces:


Overview Papers:


Recent Web Articles (grants and tool releases):


Asynchronous Design in the News...:


Research Team:

Back row (left to right): Yu Chen, Kshitij Bhardwaj, Steve Nowick, Christos Vezyrtzis, Weiwei Jiang

Front row (left to right): Adil Sadik, George Faldamis

Current PhD Students:

Kshitij Bhardwaj

Weiwei Jiang

Kunal Mahajan
 

Current Collaborating PhD Students:

Alberto Ghiribaldi (University of Ferrara [D. Bertozzi group])

Gabriele Miorandi (University of Ferrara [D. Bertozzi group])
 

Current MS Project Students:

Ankit Pradhan (Comp Eng)
 

Former Post-Doctoral Research Scientists:

Gennette Gill (D.E. Shaw Research Laboratory, New York, NY)
 

Former PhD Students:

Christos Vezyrtzis (Research Staff Member, IBM T.J. Watson Research Center, Yorktown, NY)

Melinda Agyekum (Program Manager, Enterprise Storage Backend, Google, New York, NY)

Peggy McGee (senior R&D engineer, Power Compiler group, Synopsys Corporation, Sunnyvale, CA)

Cheoljoo Jeong (staff R&D engineer, Verification group, Synopsys Corporation, Mountain View, CA; formerly senior design engineer, Cadence Design Systems, Sunnyvale, CA)

Cheng-Hong Li (became student of Prof. Luca Carloni, now NEC Research Laboratories)

Tiberiu Chelcea (formerly Postdoctoral Fellow, CS Department, CMU)

Michael Theobald (Researcher, D.E. Shaw Research Laboratory, New York, NY; formerly Postdoctoral Fellow, CS Department, CMU)

Montek Singh (Associate Professor, CS Department, University of North Carolina - Chapel Hill)

Robert Fuhrer (IBM T.J. Watson Research Center, Yorktown, NY )

Yu Chen (EE, became student of Prof. Yannis Tsividis)
 

Former MS Students: (partial list)

Sumedh Attarde (Server Design group, Intel Corporation, Santa Clara, CA)

Clementine Barbet (Comp Eng)

Marco Cannizzaro (MS co-advisor; from Politecnico di Torino, Italy)

Walter Dearing

Georgios (George) Faldamis (Cavium, Inc.)

Michael Horak [U. of Maryland, co-chair of MS thesis committee] (Advanced Simulation Technology, Inc.)

Roopa Kakarlapudi

Kiran Kumar Mada

Geoffray Lacourba (ARM Ltd., France)

Amitava Mitra (Intel India)

Ashwath Narasimhan

Harsh Parekh

Adil Sadik

Srikanth Viswanathan

Wei Wei (CDM verification engineer, CPU design and verification team, Apple Corporation)
 

Former Undergraduate Project Students: (partial list)

Steven Callender (UC Berkeley, PhD Student)

Matthew Carlberg

David Hughes

William Liu

William McLaughlin

Charles O'Donnell (MIT, PhD Student)


Teaching:

Spring 13:  CSEE E6861 Computer-Aided Design of Digital Systems

Course Advertisement:   (click here)

Detailed Course Overview:   (click here) Class Web Page:   http://www.cs.columbia.edu/~cs6861

Fall 12:  CSEE W4823 Advanced Logic Design

Course Advertisement:   (click here)

Detailed Course Overview:   (click here) Class Web Page:   http://www.cs.columbia.edu/~cs4823


Office Hours:

Spring-13: Tuesday 2:00-3:00pm, Wednesday 2:45-3:45pm

Room 508, Computer Science Building

phone: (212) 939-7056


ASYNCHRONOUS CAD TOOL PACKAGES

"The CaSCADE Package" is our new asynchronous design environment, including six different tools and libraries. The acronym "CaSCADE" = "Columbia University and University of Southern California Asynchronous Design Environment". It was developed under NSF ITR Award No. NSF-CCR-0086036, with support from additional grants (see CaSCADE web pages for details). This set of asynchronous CAD tools is available for free download for use with Linux platforms.

Three of the tools in the CaSCADE package were developed and maintained by our Columbia asynchronous research group: (a) "MINIMALIST" for asynchronous controllers; (b) the "ATN_OPT Toolset" for robust asynchronous threshold networks; and (c) the "DES (Discrete Event System) Analyzer" for performance analysis and timing verification of concurrent systems.

  • (b) The ATN_OPT Toolset, release v0.1: The "ATN_OPT" Toolset is a comprehensive CAD package for the automated synthesis and optimization of robust dual-rail asynchronous threshold networks. It supports circuit descriptions in several common formats (Verilog/VHDL/BLIF), and supports cell libraries defined in GENLIB format. It allows several user-specified optimization targets: area, delay, power, and delay-area tradeoffs. It also includes a user shell. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download ATN_OPT (including tutorial slides and setup instructions), available for Linux platforms.

    Go to the "CaSCADE" web page to download this tool (click here)

  • (c) The DES (Discrete Event System) Analyzer, release v0.1: The "DES Analyzer" is a comprehensive CAD package for performance analysis and timing verification of concurrent digital systems. It includes two tools: (i) "DES-PERF" which uses user-supplied stochastic information to compute asymptotic system performance, and (ii) "DES-TSE", which uses user-supplied min/max delay bounds on individual events to compute the global min/max "time-separation-of events" between any two pairs of events. The DES-TSE tool is especially useful in determining which orderings of concurrent events are impossible in the actual global evolution of a concurrent system (going from startup to steady-state) -- potentially useful for optimizing the system -- as well as providing min/max bounds on the system's cycle time (and hence min/max bounds on system throughput). The tool accepts system specifications in the form of a restricted classof Petri net (i.e. "marked graph"), and includes several user options, graphical interfaces, and detailed output reports. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download the DES Analyzer (and tutorial slides and setup instructions), available for Linux platforms.

    Go to the "CaSCADE" web page to download this tool (click here)