STEVEN M. NOWICK

Office:

                Department of Computer Science
                Columbia University
                508 Computer Science Building; Mail Code: 0401
                1214 Amsterdam Avenue
                New York, NY 10027

Phone: (212) 939-7056
FAX: (212) 666-0140

E-mail: nowick@cs.columbia.edu

I am a Professor of Computer Science and Electrical Engineering, and a member of the Computer Engineering Program, at Columbia University. I received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University in 1976.

My main research interests are: asynchronous digital circuits, VLSI CAD (computer-aided digital design), low-power and high-performance digital design, logic synthesis, and formal hardware verification.

Short CV

Introduction to Asynchronous Design + Overview of My Research: (PDF) [click to download slides ]

Introduction: Asynchronous Circuits and Systems -- survey articles

"Columbia Engineering News": Cover Story on My 2 Medium-Scale NSF ITR Awards (Fall 2000)

Complete List of Publications (last update: July 2001)

Asynchronous Design in the News...:

"Faster Chips That March to Their Own Improvised Beat (click here): Article in the New York Times, Circuits Section (August 22, 2002). Includes an interview with Professor Nowick.

"It's Time for Clockless Chips (click here): Cover story in Technology Review Magazine (based in MIT), October 2001, vol. 104:8 (pp. 36-41). Includes an interview with Professor Nowick.

"ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor" (from ARM Ltd. web page, Oct. 2004)

Clockless Computing: Coordinating Billions of Transistors (Washington University 150th Anniversary Symposium) (click here): Washington University Symposium, St. Louis, Missouri (March 26, 2004). Includes an invited presentation by Professor Nowick.

"Designers Look to Take Computer Chips Off the Clock" (click here): Article in Newsfactor Network (September 18, 2001) on goals and recent achievements of asynchronous design.

"Computing Pioneer Challenges the Clock" (click here) : Article in the New York Times (March 5, 2001) on Ivan Sutherland's group at Sun Microsystems Lab, and their recent advances in developing high-speed asynchronous circuits.

"Old Tricks for New Chips" (click here): Article in The Economist (April 19, 2001) on the promise of asynchronous circuits.

Columbia Asynchronous Circuits and Systems Group:
For the home page of our research group, click here.

ASYNCHRONOUS TOOL PACKAGES

"The CaSCADE Package" is our new asynchronous design environment, including six different tools and libraries. The acronym "CaSCADE" = "Columbia University and University of Southern California Asynchronous Design Environment". It was developed under NSF ITR Award No. NSF-CCR-0086036, with support from additional grants (see CaSCADE web pages for details).

Three of the tools in the CaSCADE package were developed and maintained by our Columbia asynchronous research group: (a) "MINIMALIST" for asynchronous controllers; (b) the "ATN_OPT Toolset" for robust asynchronous threshold networks; and (c) the "DES (Discrete Event System) Analyzer" for performance analysis and timing verification of concurrent systems.

(a) The MINIMALIST CAD Package, release v2.0: "MINIMALIST" is a comprehensive CAD package for the automated synthesis and optimization of asynchronous controllers. It includes a Verilog back-end, multi-level logic optimizer, decomposition tool for large specifications, verifier, online help and graphical interfaces. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download Minimalist (including extensive tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(b) The ATN_OPT Toolset, release v0.1: The "ATN_OPT" Toolset is a comprehensive CAD package for the automated synthesis and optimization of robust dual-rail asynchronous threshold networks. It supports circuit descriptions in several common formats (Verilog/VHDL/BLIF), and supports cell libraries defined in GENLIB format. It allows several user-specified optimization targets: area, delay, power, and delay-area tradeoffs. It also includes a user shell. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download ATN_OPT (including tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

(c) The DES (Discrete Event System) Analyzer, release v0.1: The "DES Analyzer" is a comprehensive CAD package for performance analysis and timing verification of concurrent digital systems. It includes two tools: (i) "DES-PERF" which uses user-supplied stochastic information to compute asymptotic system performance, and (ii) "DES-TSE", which uses user-supplied min/max delay bounds on individual events to compute the global min/max "time-separation-of events" between any two pairs of events. The DES-TSE tool is especially useful in determining which orderings of concurrent events are impossible in the actual global evolution of a concurrent system (going from startup to steady-state) -- potentially useful for optimizing the system -- as well as providing min/max bounds on the system's cycle time (and hence min/max bounds on system throughput). The tool accepts system specifications in the form of a restricted classof Petri net (i.e. "marked graph"), and includes several user options, graphical interfaces, and detailed output reports. Click below to access the web page of the "CaSCADE" asynchronous tool package, where you can download the DES Analyzer (and tutorial slides and setup instructions), available for Linux platforms.
Go to the "CaSCADE" web page to download this tool (click here)

Teaching:
Fall 05: CSEE W4823 Advanced Logic Design
Class Web Page: http://www1.cs.columbia.edu/~cs4823
Spring 06: CSEE W4861 Computer-Aided Design of Digital Systems
Course Description: (click here) Class Web Page: http://www.cs.columbia.edu/~cs4861

Current PhD Students:

Melinda Agyekum

Cheoljoo Jeong

Peggy McGee

Current MS Students:

Former PhD Students:

Cheng-Hong Li (now student of Prof. Luca Carloni)

Tiberiu Chelcea (Postdoctoral Fellow, CS Department, Carnegie-Mellon University)

Robert Fuhrer (IBM T.J. Watson Research Lab)

Montek Singh (Assistant Professor, CS Department, University of North Carolina - Chapel Hill)

Michael Theobald (Researcher, D.E. Shaw Research and Development; formerly Postdoctoral Fellow, CS Department, Carnegie-Mellon University)

Former MS Students:

Amitava Mitra (Intel India)

Link to New York State Microelectronics Design Center (MDC): (click here)