CSEE W3827 - Fundamentals of Computer Systems

Call number 24562

[Course Info][Assignments] [Discussion Board (via Courseworks)][Grading Info]

Course Information (Also available in pdf)

Professor Dan Rubenstein
Spring 2014


Contact Information
Who Office Phone E-mail Office Hours
Prof. Dan Rubenstein CEPSR 816 (212) 939-7048 danr@cs.columbia.edu W,Th 10-11am, or by appt
TA Andrew Mercer-Taylor TA Room N/A
Contact Prof and TAs: 3827TA@lists.cs.columbia.edu
Date   #   Topics/chapters covered   Reading   Assigned   Due  
1/22   1   Intro; Overview of Computer Architecture; Definitions (bit,byte,word)   M&K Ch 1      
1/27   2   Binary number representations: 1's complement; 2's complement, adding and subtracting and overflow; floating point representations: overflow and underflow   M&K 4.3-4.4, 10.7, P&H 3.5 skip FP in MIPS   HW #1    
1/29   3   Logic gates; XOR; Boolean Algebra; NAND and NOR gates; Taking complements; DeMorgan's Theorem; Duals   M&K 2.1-2.2, 2.8, 2.9      
2/3   4   Standard Forms: minterms, maxterms, sum-of-products, product-of-sums   M&K 2.3   HW #2   HW #1  
2/5   5   K-maps: simplification with implicants, Don't-care conditions   M&K 2.4-2.5      
2/10   6   *** Catchup ***     HW #3   HW #2  
2/12   7   Combinatorial Circuit Design: Multi-bit output functions; standard combinatorial circuits (enabler, decoder, encoder, priority encoder, mux   M&K 3.1, 3.3, 3, 3.6-3.9      
2/17   8   Arithmetic funcs: Adder (half, full, ripple-carry, adder-subtractor); Contraction; Shifter   M&K 4.1-4.2, 4.5, 9.4   HW #4   HW #3  
2/19   9   Sequential Circuitry: Latch, Flip-Flops, timing issues   M&K 5.1-5.3, 5.6      
2/24   10   Sequential Circuit Analysis & Design: State machines   M&K 5.4-5.5   HW #5   HW #4  
2/25   11   PLAs; ROM; Register Design: Load and Transfer   M&K 6.8, 7.1-7.3      
3/3   12   Register Design cont'd: MicroOps and Counters, mux and serial transfer   M&K 7.5-7.6, 7.8-7.9     HW #5  
3/5   13   Memory Design   M&K 8.1-8.7      
3/10   14   *** Catchup and/or Midterm review ***        
3/12   16   Processor Design: Datapath, ALU   M&K 9.1-9.5   HW #6    
3/17   --   SPRING BREAK - NO CLASS!        
3/19   --   SPRING BREAK - NO CLASS!        
3/24   17   Control Word; Simple Arch; Instruction Decoder   M&K 9.6-9.8   HW #7   HW #6  
3/26   15   MIDTERM (in class)        
3/31   18   Instruction Types and Formats   P&H 2.1-2.6      
4/2   19   Branches, stacks, heaps, immediate addressing   P&H 2.7-2.8, 2.10   HW #8   HW #7  
4/7   20   Single Cycle Datapath   P&H 4.1-4.4      
4/9   21   Single Cycle Datapath cont'd     HW #9   HW #8  
4/14   22   Pipelining   P&H 4.5-4.6      
4/16   23   Hazards   P&H 4.7-4.8      
4/21   24   Cache & Cache Replacement Policies   P&H 5.1-5.2      
4/23   25   *** Catchup and/or review ***       HW #9  
4/28   26   *** Catchup and/or review ***        
4/30   26   *** Catchup and/or review ***        
5/5   26   *** Catchup and/or review ***        
Tentative 5/12     FINAL EXAM, Time 1:10pm-4:10pm   Location TBD      

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