The text is now available in the bookstore (Papyrus). ***Make sure that you get the SECOND edition.***
READ: Chapter 1 (Introduction) and Appendix B.1 and B.2 (Logic Design).
PROBLEMS: In text: Appendix B/(1, 4-6, 8, 10 (first 3 parts), 14).
Read: Appendix B, except for B.7
Problems: B/(11 [omit part 4], 12 [omit part 2], 18, 20-22).
Nontext:
NT1. Draw circuit for a 1-8 deMUX using as components, 1-2 deMUX's
NT2. For the example worked out on p. B-17, show that a better solution exists: 3 discrete 2-input gates, and that only 3 PLA product terms are necessary.
NT3. Using only AND-gates and inverters, construct a minimal circuit realizing a 3-5 decoder. Take full advantage of the don't cares generated by the assumption that the only allowed input states are those corresponding to the binary numbers ranging from 0 to 100.
OPTIONAL: Using 2-1 MUX's as components, implement a 5-1 MUX.
Problems: Text, 4/(1-8, 11)
Nontext: Using 2-input XOR-gates, design a circuit to generate a parity bit for an 8-bit word. Then design a circuit whose output is 1 if an odd number of bits are corrupted in a 9-bit (including the parity bit) word generated by the previous circuit.
Read: 4.3-4.5 (thru p. 240), Chapter 3 thru 3.5.
Problems: 4/23.
NT-1. Show how we can add to the capabilities of the ALU discussed in class and in the text a command for generating the Boolean complement of input B.
NT-2. Repeat NT-1, but with the new operation being to generate the absolute value of input B. Assume that we can easily generate a 1-bit control signal ABS that is 1 when the ALU control input corresponds to the absolute value command. Don't forget to consider the case where B is the negative number with the greatest absolute value.
READ: 3.6-3.8.
PROBLEMS: 3/(4-6, 9-11, 29, 30)
Read: Appendix A, finish Chapter 3.
Problems: 3/(12, 21-24, 26), 4/21
Read: 4.6, 4.8-4.11
Problems: Text 4/(25-28, 31)
NonText problems: Assume a conventional (non-Booth) add-and-shift multiplier for 4-bit numbers, but modify it by using ARITHMETIC shifts.
NT1. Suppose now we check this out for twos complement (TC) arithmetic. What is the result if the multiplicand is 1011, a negative number, and the multiplier is 0101? Is this the correct product? What if 1011 is the multiplier and 0101 is the multiplicand? Is this correct?
NT2. Now modify the multiplier further by adding the condition that the leftmost bit of the multiplier is assigned a negative weight, so that for the last step in the process, if the multiplier bit is one, the multiplicand is SUBTRACTED instead of added. Try this out for the two situations specified in NT1. Are the multiplier results correct?
Read: 5/(1-4, 5[scan], 6), 6/(1-3)
Problems: 5/29, 6/(2, 3, 4, 11, 12)
Read: 6/(4-7), 7/(1, 2)
Problems: 6/(14, 15), 7/(7-10, 13)
Read: B.5, 7.4
Problems: 7/(15, 16, 24, 25, 27, 32)
NON-TEXT PROBLEM:
Consider the design of a DRAM chip with 4 M addressable 4-bit words. Assume that it is important, for manufacturing reasons, that the chip be as near square as possible, so that the number of element rows be the same as the number of element columns. How many rows and columns will there be? How many bits are in the row-address? How many bits are in the column address? Considering only read-out, specify the number and sizes of MUX's, and decoders on the chip.
Read: 7.5-7.8, 8/(1-4)
Problems: 8.3, 7/(33, 34, 38)