SOLUTIONS FOR MIDTERM EXAMINATION
Computer Science W3823 October 18, 2001
1. (8 pts) In the circuit below, find Vout , the voltage across the 3K
resistor, to 3 significant figures.reat as voltage divider. Let
a||b mean resistance of the parallel combination of a and b.
2||3 = (2x3)/(2+3)= 6/5 So Vout=((6/5)/(6/5+2))x6= 6x6/(10+6)=6x6/16=
9/4=2.25v .
Another way to solve this problem is to find the total resistance (as
above, 2+6/5=3.2K), then the current flowing out of the voltage
source, all of which flows thru the upper 2K resistor. This is
6/(16/5)= 30/16=15/8mA. Then multiply this current by 2K to find
the voltage across the upper 2K resistor. This is 30/8=15/4v.
Subtract this from 6 to get the output voltage.
When doing such calculations by hand, one should take the easy route,
by simplifying fractions. Final results should be presented in
proper form, NOT left as arithmetic problems. If uncertain as to
what the proper form is, review the website piece on numbers.
2. (12 pts) For the circuit below, assume S has been open for a long
time and then is closed at time
t = 0.
First combine the two parallel capacitors, by adding their values to
get an equivalent single capacitor with value 0.06pf
(a) Immediately after S is closed, the charge stored in the capacitor,
and hence the voltage across the capacitor cannot change instantly,
so it is the same as the value just before S closes. This is
simply 6v.
(b) After S has been closed for a long time, the capacitor will be
charged to the voltage that would appear across it if it were
replaced by an open circuit. This is the voltage across the 4K
resistor, which is in series with the 2K resistor and the voltage
source. (Again a voltage divider problem.) So Vc=4x6/(4+2)=4v.
(c) The resistance part of the time constant is found by computing the
resistance seen by the capacitor when the voltage source is
replaced by a short circuit. This is the parallel combination of
the 4K and 2K resistors, which is 4x2/(4+2)=4Kx2/6. So
T=RC=(4x2x10^3x0.06x10^-12)/6
=8x10^-11s. Again, such answers should be written in appropriate
form.
(d) In general, Vc=Vcf-(Vcf-Vcin)e^t/T. So, in this case we have
Vc=4-(4-6)e^-t/8x10^-11=4+2e^t/8x10-11
It is NOT acceptable on an exam, or in the real world, to present such
a result in intermediate form such as Vc=4-(4-6)e^-t/8x10^-11.
3. (8 pts) This is a NOR-gate, so, if V1 is hi, Vout is lo, which, for
a CMOS gate, is 0v.
Since the resistance from the transistor gate to ground is extremely
hi, no significant current can flow into the gate, so i=0. Note
the resemblance of part b of this problem to that given for HW
(A.23 in the text) and discussed in class.
4. (8 pts) Z = A(B'+C)+A'B. When A=0, Z=1 when B=1, so there are 1's
for rows 010 and 011. When A=1, Z=1 when B=0 or when C=1, so we
also have 1's in rows 100, 101, and 111. There are 0's in the
remaining rows, namely, 000, 001, and 110.
5. (8 pts) Which, if any, of the expressions below is a minimal POS
(product of sums) expression for A(B' + CD) + C'? Use identity
X+f(X)=X+f(0) to simplify the expression to
A(B + D) + C . Now use adding out to get (A+C')(B'+D+C'),
corresponding to answer (a).
6. (8 pts) Which, if any, of the logic expressions a-f describes the
function realized by the circuit?
The internal inverter and the inverter at the B input cancel out. The
two B-inputs cancel and the two C-inputs cancel. This leaves
A(+)D, answer (f). A key identity here is X(+)X=0.
7. (8 pts) Which, if any, of the expressions for Z below corresponds
to the following NAND-gate circuit? Convert the rightmost gate to
an equivalent gate consisting of an OR-gate with both inputs
inverted. These input inverters cancel the inverters at the
outputs of the 2 NAND-gates feeding the last gate, so we have two
AND-gates feeding an OR-gate. Convert the leftmost NAND-gate to
an OR-gate with inverters at the inputs. So the output of this
gate can be seen to be E+F. Now we see the expression
corresponding to the overall circuit is: ABC+D(E+F), which is
answer (b).
8. (8 pts.) Using Boolean algebra theorems, determine which of the
expressions below, if any, is a minimal SOP expression for the
function described by Z = A'B' + C'D + (A + B)C +DEF
First note that A'B'=(A+B)'. Since we have a term (A+B)C, we can use
the identity X+X'Y=X+Y to reduce the expression to Z = A'B' + C'D
+ C +DEF. Using this identity again on C'D + C, we obtain Z =
A'B' + D + C +DEF. Now apply the identity X+XY=X to D+DEF to
obtain Z = A'B' + D + C, which is answer (b)
9. (8 pts) Write a minimal SOP expression that describes the function
realized by the circuit below?
Let g be the function realized at the output of the left transmission
gate. If A=0, g=0 (the T-gate is open and pulldown transistor
pulls the output down to 0). If A=1, the T-gate transmits C, so
the output is C. So g=AC. Similarly, the output of the right
T-gate is Bg=ABC. So the function realized is ABC.
10.(8 pts) Which, if any, of the expressions a-f below is equivalent
to the dual of Z = AB'(C + DE')? Which, if any, specifies the
complement of the given expression?
Interchanging + and x yields the dual expression, A+B'+C(D+E'),
answer (c)
Complementing all the literal in the dual expression yields the
complement, A'+B+C'(D'+E), answer (f)
11. (8 pts) Write a logic expression corresponding directly to the
transmission of the switching circuit below.
There are two main parallel branches, the lower of which has
transmission D'. Add to this the transmission of the upper
branch, which consists of A in series with 2 parallel branches.
Now we have T=D'+A(tr of parallel branches). Analyzing the lesser
parallel branches, we find the transmission of this combination to
be C'+BE, so the resulting overall transmission is T=D'+A(C'+BE)
12. (8 pts) On the 4-variable K-map below, map the function described
by the expression
Z = A(B + D) + A (D + C)
One approach is to multiply out and then plot each product term. Or
we can observe that, in the left half of the map, corresponding to
the A' region, there are 1's in the C-region (lower 2 rows) and in
the D' region (top and bottom rows). Then, in the right half of
the map (the A-region), there are 1's in the B' half (right
column) and in the d-region (middle two rows). Thus we obtain the
mapping shown below (where 0's are inserted in the blank cells of
the map).
1101
0011
1111
1101
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EXAM STATISTICS:
Grade range: 30-100 Average: 71 Median: 75 SD: 20
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