| Sunday, October 12 |
| 6:00 PM - 8:00 PM : Welcome Reception, Sheraton University City |
| Monday, October 13 |
| 9:00 AM - 9:50 AM : Invited Session |
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Emerging trends in adaptive middleware and its application to distributed real-time embedded systems
Joseph P. Loyall (BBN Technologies, USA) Abstract Embedded systems have become prevalent in today's computing world and more and more of these embedded systems are highly distributed and network centric. This adds increasing degrees of resource contention, unpredictability, and dynamism to software that has traditionally been designed with resources being provisioned statically and for the worst case. This paper describes the research that we've been doing in the development of middleware for QoS adaptive systems - an extension to standard off-the-shelf distributed object middleware - and its application to two military distributed real-time embedded systems. These real-world evaluations of the technology then motivate a discussion of the next directions in which we are taking this research. |
| 9:50 AM - 10:15 AM : Coffee Break |
| 10:15 AM - 12:15 AM : Programming Languages |
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Translating Discrete-Time Simulink to Lustre
Paul Caspi, Adrian Curic, Aude Maignan, Christos Sofronis, and Stavros Tripakis (VERIMAG, France) |
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Clocks as First Class Abstract Types
Jean-Louis Colaco (Esterel Technologies, France) and Marc Pouzet (Laboratoire LIP6, France) |
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Clock-Driven Automatic Distribution of Lustre Programs
Alain Girault (INRIA, France) and Xavier Nicollin (INPG - Verimag, France) |
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Generating Heap-Bounded Programs in a Functional Setting
Walid Taha, Stephan Ellner (Rice University, USA), and Hongwei Xi (Boston University, USA) |
| 12:15 PM - 2:00 PM : Lunch Break |
| 2:00 PM - 2:50 PM : Invited Session |
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Resource-Efficient Scheduling for Real Time Systems
Kim G Larsen (Aalborg University, Denmark) Abstract For embedded systems efficient utilization of resources is an acute problem arising from the increasing computational demands in all sorts of applications: the constant consumers demand for better functionality and flexibility of embedded products imply an increase in the resources needed for their realisation. In several areas -- e.g. portable devices such as PDAs, mobile phones and laptops as well as mission critical systems such as space applications -- the ability to design resource efficient solutions is crucial. In this talk we will present work on development and applications of the real-time verification tool UPPAAL to the modelling, analysis and synthesis of resource-efficient and -optimal scheduling for real-time systems. Whereas (hard) timeliness and resource-efficiency may be seen as conflicting goals, this approach allows for both goals to be achieved. Emphasis will be given to the application of UPPAAL to two industrial case studies focusing on memory management and utilization and power/energy consumption respectively. The first case study is provided by Terma A/S who is developing and producing radar sensor equipment. The case study, conducted in the IST AMETIST project, focuses on the memory interface of the video processing board of a radar sensor system used for ground surveillance at airports and for coastal surveillance. The task of the memeory interface is to control access to a single memory bus used by 9 different (buffered) data streams. A valid scheduler must guarantee that none of the data streams are ever interrupted, and efficiency is measured in the requirement to buffer sizes. The second case study focusses on Dynamic Voltage Scaling, which appears as one of the most promissing methods for reducing energy consumption. The principle consists in dynamically adjusting the clock-cycle length as well as the supply voltage depending on the actually task load in the system. However, optimality depends highly on the concrete hardware platform as well as the type of applications. Within the newly formed danish center for embedded software systems, CISS, and in collaboration with Analog Devices various DVS scheduling principles are modelled, simulated and analysed, with Analog Dvices Blackfin DSP processor (ADSP-21535 EZ-KIT Lite) as ultimate target. |
| 2:50 PM - 3:15 PM : Coffee Break |
| 3:15 PM - 5:15 PM : Modeling Techniques |
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Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment
Albert Benveniste (IRISA/INRIA, France), Luca Carloni (UC Berkeley, USA), Paul Caspi (Verimag, France), and Alberto Sangiovanni-Vincentelli (UC Berkeley, USA) |
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Constraint-Based Design-Space Exploration and Model Synthesis
Sandeep Neema, Janos Sztipanovits, Gabor Karsai (Vanderbilt University/ISIS, USA), and Ken Butts (Ford Motor Co, USA) |
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A methodology and tool support for generating scheduled native code for real-time Java applications
Christos Kloukinas, Chaker Nakhli, and Sergio Yovine (Verimag, France) |
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Resource Interfaces
Arindam Chakrabarti (UC Berkeley, USA), Luca de Alfaro (UC Santa Cruz, USA), Thomas Henzinger (UC Berkeley, USA), and Marielle Stoelinga (UC Santa Cruz, USA) |
| 5:15 PM - 7:00 PM : ACM SIGBED Business Meeting |
| 7:30 PM - : Banquet at University of Pennsylvania Museum of Archaelogy |
| Tuesday, October 14 |
| 9:00 AM - 9:50 AM : Invited Session |
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CAD for embedded system design in the era of billion transistor chips
Greg Spirakis (Intel, USA) Abstract Recent advances in silicon fabrication technologies, clearly suggest that Moore's law will continue to hold for at least the next 10-20 years. During this timeframe we will progress from the 90nm technology node, to the 65nm node and beyond, making billion transistor chips feasible. As fabrication technologies move forward, the landscape in CAD tool development will have to be reshaped to accommodate the two main areas of challenges that are bound to appear. On the one hand, our future physical design tools will have to tackle many difficult technical issues that are related to the fundamental physical phenomena which dictate the behavior of circuit structures at such small feature sizes. On the other hand, for the front end of the design, the CAD tools will have to accommodate designing systems at a much higher level of abstraction. This will be absolutely necessary if we are to effectively exploit the computational power that an ever increasing number of transistors will be providing. For increased productivity during the design of systems with that many transistors, one will have to re-use IP blocks extensively and take into account the interplay between the software and the hardware that will be executing it. Embedded system design has traditionally focused on these problems and provided solutions that address them with varying degrees of success. Going forward, it is important that we see CAD vendors and Academia provide more complete solutions in this field. In this talk we will describe the problems in embedded system design that seem relevant from the Intel business perspective such as functionality partitioning and low power design. Finally, we will describe in detail the common projects that we have undertaken with our Academic research partners for solving them. |
| 9:50 AM - 10:15 AM : Coffee Break |
| 10:15 AM - 12:15 AM : Resource-aware Systems |
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Energy-Conscious Memory Allocation and Deallocation for Pointer-Intensive Applications
Victor De La Luz, Mahmut Kandemir, Guangyu Chen (Penn State University, USA), and Ibrahim Kolcu (UMIST, UK) |
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Intelligent Editor for Writing WCET-Oriented Programs
Janosch Fauster, Raimund Kirner, and Peter Puschner (Vienna University of Technology, Austria) |
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HOKES/POKES: Light-weight resource sharing
Herbert Bos and Bart Samwel (University of Leiden, Netherlands) |
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Energy-Efficient Multi-Processor Implementation of Embedded Software
Gang Qu (Univ. of Maryland, College Park, USA) |
| 12:15 PM - 2:00 PM : Lunch Break |
| 2:00 PM - 2:50 PM : Invited Session |
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From Spaghetti to Raviolli -- Componet-izing the LaserJet Firmware
Keith Moore (HP Labs, USA) Abstract A LaserJet is a fascinating distributed embedded system. A common deployment will have 5 processors, 4 different operating systems, be written in 3 programming languages, supporting 32 threads, with no virtual memory. Even the lowest-end product has significant hardware assist/ASICs to turn a general purpose processor into a screaming imaging pipeline. The system is difficult to monitor, understand, characterize, much less debug. Cost optimization (driven by business needs) creates a tension between exquisite engineering and falling over the out-of-memory/out-of-bandwidth cliff. Critical issues are budgeting modules, isolating defects, supporting graceful failure, while enabling over 100 engineers to work simultaneously on the same codebase. In this talk, I'll outline the challenges (both technical and business) in the complex embedded (and distributed) world. |
| 2:50 PM - 3:50 PM : Compiler Techniques |
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Eliminating Stack Overflow by Abstract Interpretation
John Regehr, Alastair Reid, and Kirk Webb (University of Utah, USA) |
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Minimizing Variables' Lifetime in Loop-Intensive Applications
Noureddine Chabini and Wayne Wolf (Princeton University, USA) |
| 3:50 PM - 4:15 PM : Coffee Break |
| 4:15 PM - 5:45 PM : Panel on Emerging Applications and Technologies |
| Pradeep K. Khosla (CMU) |
| Kane K. H. Kim (UCI) |
| Jane Liu (Microsoft) |
| Jeff Pridmore (Lockheed Martin) |
| Steve Vestal (Honeywell) |
| Wednesday, October 15 |
| 9:00 AM - 9:50 AM : Invited Session |
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A probabilistic framework for schedulability analysis
Alan Burns (York University, UK) Abstract The limitations of the deterministic formulation of scheduling are outlined and a probabilistic approach is motivated. A number of models are reviewed with one being chosen as a basic framework. Response-time analysis is extended to incorporate a probabilistic characterisation of task arrivals and execution times. Copulas are used to represent dependencies. |
| 9:50 AM - 10:15 AM : Coffee Break |
| 10:15 AM - 11:45 AM : Real-Time Scheduling |
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Rate Monotonic vs. EDF: Judgment Day
Giorgio Buttazzo (University of Pavia, Italy) |
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A Hybrid Proactive Approach for Integrating Off-line and On-line Real-Time Schedulers
Weirong Wang, Aloysius Mok (University of Texas at Austin, USA), and Gerhard Fohler (Malardalen University, Sweden) |
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Schedule-Carrying Code
Thomas Henzinger, Christoph Kirsch, and Slobodan Matic (UC Berkeley, USA) |
| 11:45 AM - 1:30 PM : Lunch Break |
| 1:30 PM - 2:20 PM : Invited Session |
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Static Verification of General-Purpose Languages
Alain Deutsch (Polyspace Technologies, France) Abstract We survey the industrial results obtained by our static verification tools. We first applied our techniques to the Ariane 5 launcher embedded software in 1997, which was to our knowledge the first industrial use of program analysis techniques to static detection of runtime errors on industrial codes. A noteworthy characteristic of our approach is the fact that we work with the unannotated source code, that we deal with infinite sets of properties and that we provide sound and exhaustive results. More than 100 industrial projects now use our tools in automotive, avionics, energy, transportation and other critical systems in Europe, North America and Asia. We finally discuss connections with engineering standards such as DO-178B, or MISRA-C. |
| 2:20 PM - 2:45 PM : Coffee Break |
| 2:45 PM - 4:15 PM : Formal Methods |
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Reasoning about Abstract Open Systems with Generalized Module Checking
Patrice Godefroid (Bell Laboratories, Lucent Technologies, USA) |
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Event Correlation: Language and Semantics
Cesar Sanchez, Sriram Sankaranarayanan, Henny Sipma, Ting Zhang, David Dill, and Zohar Manna (Stanford University, USA) |
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Space Reductions for Model Checking Quasi-Cyclic Systems
Matthew Dwyer, Fnu Robby, William Deng, and John Hatcliff (Kansas State University, USA) |