---

clk

clock_source v12.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cpu_0

altera_nios2 v12.1

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Dynamic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave epcs_controller.epcs_control_port resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _10 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 1023 instSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x0' end='0x800000' /><slave name='cfi_flash_0.s1' start='0x800000' end='0x900000' /><slave name='epcs_controller.epcs_control_port' start='0x900800' end='0x901000' /><slave name='sram_0.avalonS' start='0x980000' end='0xA00000' /><slave name='cpu_0.jtag_debug_module' start='0x1000000' end='0x1000800' /></address-map> instAddrWidth 25 impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave sdram_0.s1 exceptionOffset 32 deviceFeaturesSystemInfo NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 deviceFamilyName CYCLONEII debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _4 dcache_bursts false dataSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x0' end='0x800000' /><slave name='cfi_flash_0.s1' start='0x800000' end='0x900000' /><slave name='timer_0.s1' start='0x900000' end='0x900020' /><slave name='sysid.control_slave' start='0x900020' end='0x900028' /><slave name='SEG7_Display.avalonS' start='0x900028' end='0x90002C' /><slave name='lcd_16207_0.control_slave' start='0x900030' end='0x900040' /><slave name='uart_0.s1' start='0x900040' end='0x900060' /><slave name='timer_1.s1' start='0x900060' end='0x900080' /><slave name='ISP1362.avalonS' start='0x900080' end='0x900090' /><slave name='DM9000A.avalonS' start='0x900090' end='0x900098' /><slave name='ps2_0.avalon_PS2_slave' start='0x900098' end='0x9000A0' /><slave name='led_green.s1' start='0x9000C0' end='0x9000D0' /><slave name='led_red.s1' start='0x9000D0' end='0x9000E0' /><slave name='I2C_0.avalonS' start='0x900100' end='0x900120' /><slave name='button_pio.s1' start='0x900120' end='0x900130' /><slave name='switch_pio.s1' start='0x900130' end='0x900140' /><slave name='epcs_controller.epcs_control_port' start='0x900800' end='0x901000' /><slave name='sram_0.avalonS' start='0x980000' end='0xA00000' /><slave name='binary_vga_controller_0.avalon_slave_0' start='0xA00000' end='0xC00000' /><slave name='cpu_0.jtag_debug_module' start='0x1000000' end='0x1000800' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1004000' end='0x1004008' /></address-map> dataAddrWidth 25 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 50000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 4 DCACHE_LINE_SIZE_LOG2 2 DCACHE_SIZE 2048 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x20 RESET_ADDR 0x900800 BREAK_ADDR 0x1000020 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 25 DATA_ADDR_WIDTH 25 NUM_OF_SHADOW_REG_SETS 0

---

jtag_uart_0

altera_avalon_jtag_uart v12.1

Parameters allowMultipleConnections false avalonSpec 1.0 hubInstanceID 0 legacySignalAllow true readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

---

sdram_0

altera_avalon_new_sdram_controller v12.1

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 50000000 columnWidth 8 dataWidth 16 generateSimulationModel true initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 12 size 8388608 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 1 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 22 SDRAM_ROW_WIDTH 12 SDRAM_COL_WIDTH 8 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

---

tri_state_bridge_0

altera_avalon_tri_state_bridge v12.1

Parameters registerIncomingSignals true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cfi_flash_0

altera_avalon_cfi_flash v12.1

Parameters actualHoldTime 40.0 actualSetupTime 40.0 actualWaitTime 160.0 addressWidth 20 clockRate 50000000 corePreset CUSTOM dataWidth 8 holdTime 40 setupTime 40 sharedPorts s1/data,s1/address,s1/read_n timingUnits NS waitTime 160 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments SETUP_VALUE 40 WAIT_VALUE 160 HOLD_VALUE 40 TIMING_UNITS "ns" SIZE 1048576u

---

timer_0

altera_avalon_timer v12.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1.0 periodUnits MSEC resetOutput false snapshot true systemFrequency 50000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1.0 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 50000000u LOAD_VALUE 49999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

sysid

altera_avalon_sysid v12.1

Parameters id 2107934667 timestamp 1360638404 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 2107934667u TIMESTAMP 1360638404u

---

uart_0

altera_avalon_uart v12.1

Parameters baud 115200 baudError 0.01 clockRate 50000000 dataBits 8 fixedBaud true parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 115200 DATA_BITS 8 FIXED_BAUD 1 PARITY 'N' STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0 SIM_TRUE_BAUD 0 SIM_CHAR_STREAM "" FREQ 50000000u

---

timer_1

altera_avalon_timer v12.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1.0 periodUnits MSEC resetOutput false snapshot true systemFrequency 50000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1.0 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 50000000u LOAD_VALUE 49999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

lcd_16207_0

altera_avalon_lcd_16207 v12.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

led_green

altera_avalon_pio v12.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 9 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 9 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

---

led_red

altera_avalon_pio v12.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 18 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 18 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

---

button_pio

altera_avalon_pio v12.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 50000000 direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "FALLING" IRQ_TYPE "EDGE" FREQ 50000000u

---

switch_pio

altera_avalon_pio v12.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 18 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 18 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

---

SEG7_Display

user_logic_SEG7_LUT_8_classic v2.0

Parameters instancePTF MODULE SEG7_Display { class = "user_logic_SEG7_LUT_8"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "0"; Data_Width = "32"; Has_IRQ = "0"; Has_Base_Address = "1"; Read_Wait_States = "0ns"; Write_Wait_States = "0ns"; Setup_Time = "0ns"; Hold_Time = "0ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00900028"; Address_Group = "0"; } PORT_WIRING { PORT oSEG0 { width = "7"; direction = "output"; type = "export"; } PORT oSEG1 { width = "7"; direction = "output"; type = "export"; } PORT oSEG2 { width = "7"; direction = "output"; type = "export"; } PORT oSEG3 { width = "7"; direction = "output"; type = "export"; } PORT oSEG4 { width = "7"; direction = "output"; type = "export"; } PORT oSEG5 { width = "7"; direction = "output"; type = "export"; } PORT oSEG6 { width = "7"; direction = "output"; type = "export"; } PORT oSEG7 { width = "7"; direction = "output"; type = "export"; } PORT iDIG { width = "32"; direction = "input"; type = "writedata"; } PORT iWR { width = "1"; direction = "input"; type = "write"; } PORT iCLK { width = "1"; direction = "input"; type = "clk"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "oSEG0"; radix = "hexadecimal"; } SIGNAL b { name = "oSEG1"; radix = "hexadecimal"; } SIGNAL c { name = "oSEG2"; radix = "hexadecimal"; } SIGNAL d { name = "oSEG3"; radix = "hexadecimal"; } SIGNAL e { name = "oSEG4"; radix = "hexadecimal"; } SIGNAL f { name = "oSEG5"; radix = "hexadecimal"; } SIGNAL g { name = "oSEG6"; radix = "hexadecimal"; } SIGNAL h { name = "oSEG7"; radix = "hexadecimal"; } SIGNAL i { name = "iDIG"; radix = "hexadecimal"; } SIGNAL j { name = "iWR"; } SIGNAL k { name = "iCLK"; } SIGNAL l { name = "iRST_N"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SEG7_LUT.v,__PROJECT_DIRECTORY__/SEG7_LUT_8.v, __PROJECT_DIRECTORY__/SEG7_Display.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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sram_0

user_logic_SRAM_16Bits_512K_classic v2.0

Parameters instancePTF MODULE sram_0 { class = "user_logic_SRAM_16Bits_512K"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "dynamic"; Address_Width = "18"; Data_Width = "16"; Has_IRQ = "0"; Has_Base_Address = "1"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; Is_Memory_Device = "1"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00980000"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } PORT_WIRING { PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT iADDR { width = "18"; direction = "input"; type = "address"; } PORT iWE_N { width = "1"; direction = "input"; type = "write_n"; } PORT iOE_N { width = "1"; direction = "input"; type = "outputenable_n"; } PORT iCE_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT iUB_N { width = "1"; direction = "input"; type = "byteenable_n"; } PORT iLB_N { width = "1"; direction = "input"; type = "byteenable_n"; } PORT SRAM_DQ { width = "16"; direction = "inout"; type = "export"; } PORT SRAM_ADDR { width = "18"; direction = "output"; type = "export"; } PORT SRAM_UB_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_LB_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_WE_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_CE_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_OE_N { width = "1"; direction = "output"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "oDATA"; radix = "hexadecimal"; } SIGNAL b { name = "iDATA"; radix = "hexadecimal"; } SIGNAL c { name = "iADDR"; radix = "hexadecimal"; } SIGNAL d { name = "iWE_N"; } SIGNAL e { name = "iOE_N"; } SIGNAL f { name = "iCE_N"; } SIGNAL g { name = "iRST_N"; } SIGNAL h { name = "iUB_N"; } SIGNAL i { name = "iLB_N"; } SIGNAL j { name = "SRAM_DQ"; radix = "hexadecimal"; } SIGNAL k { name = "SRAM_ADDR"; radix = "hexadecimal"; } SIGNAL l { name = "SRAM_UB_N"; } SIGNAL m { name = "SRAM_LB_N"; } SIGNAL n { name = "SRAM_WE_N"; } SIGNAL o { name = "SRAM_CE_N"; } SIGNAL p { name = "SRAM_OE_N"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SRAM_16Bit_512K.v, __PROJECT_DIRECTORY__/sram_0.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

I2C_0

user_logic_Open_I2C_classic v2.0

Parameters instancePTF MODULE I2C_0 { class = "user_logic_Open_I2C"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "3"; Data_Width = "8"; Has_IRQ = "1"; Has_Base_Address = "1"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; Setup_Time = "0"; Hold_Time = "0"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "6"; } Base_Address = "0x00900100"; Address_Group = "0"; } PORT_WIRING { PORT wb_clk_i { width = "1"; direction = "input"; type = "clk"; } PORT wb_rst_i { width = "1"; direction = "input"; type = "always0"; } PORT arst_i { width = "1"; direction = "input"; type = "reset_n"; } PORT wb_adr_i { width = "3"; direction = "input"; type = "address"; } PORT wb_dat_i { width = "8"; direction = "input"; type = "writedata"; } PORT wb_dat_o { width = "8"; direction = "output"; type = "readdata"; } PORT wb_we_i { width = "1"; direction = "input"; type = "write"; } PORT wb_stb_i { width = "1"; direction = "input"; type = "chipselect"; } PORT wb_cyc_i { width = "1"; direction = "input"; type = "chipselect"; } PORT wb_ack_o { width = "1"; direction = "output"; type = "waitrequest_n"; } PORT wb_inta_o { width = "1"; direction = "output"; type = "irq"; } PORT scl_pad_i { width = "1"; direction = "input"; type = "export"; } PORT scl_pad_o { width = "1"; direction = "output"; type = "export"; } PORT scl_padoen_o { width = "1"; direction = "output"; type = "export"; } PORT sda_pad_i { width = "1"; direction = "input"; type = "export"; } PORT sda_pad_o { width = "1"; direction = "output"; type = "export"; } PORT sda_padoen_o { width = "1"; direction = "output"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "wb_clk_i"; } SIGNAL b { name = "wb_rst_i"; } SIGNAL c { name = "arst_i"; } SIGNAL d { name = "wb_adr_i"; radix = "hexadecimal"; } SIGNAL e { name = "wb_dat_i"; radix = "hexadecimal"; } SIGNAL f { name = "wb_dat_o"; radix = "hexadecimal"; } SIGNAL g { name = "wb_we_i"; } SIGNAL h { name = "wb_stb_i"; } SIGNAL i { name = "wb_cyc_i"; } SIGNAL j { name = "wb_ack_o"; } SIGNAL k { name = "wb_inta_o"; } SIGNAL l { name = "scl_pad_i"; } SIGNAL m { name = "scl_pad_o"; } SIGNAL n { name = "scl_padoen_o"; } SIGNAL o { name = "sda_pad_i"; } SIGNAL p { name = "sda_pad_o"; } SIGNAL q { name = "sda_padoen_o"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/i2c_master_bit_ctrl.v,__PROJECT_DIRECTORY__/i2c_master_byte_ctrl.v,__PROJECT_DIRECTORY__/i2c_master_defines.v,__PROJECT_DIRECTORY__/i2c_master_top.v, __PROJECT_DIRECTORY__/I2C_0.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

epcs_controller

altera_avalon_epcs_flash_controller v12.1

Parameters autoSelectASMIAtom true clockRate 50000000 deviceFamilyString CYCLONEII useASMIAtom true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_OFFSET 512

---

ISP1362

altera_avalon_user_defined_interface_classic v7.0.8121

Parameters instancePTF MODULE ISP1362 { class = "altera_avalon_user_defined_interface"; class_version = "6.05"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Imported_Wait = "0"; Nios_Gen_Waits = "1"; Simulate_Imported_HDL = "1"; Port_Type = "Avalon Slave"; HDL_Import = "1"; Timing_Units = "ns"; Unit_Multiplier = "1"; Setup_Value = "200"; Hold_Value = "200"; Wait_Value = "100"; Address_Width = "32"; Module_List = ""; Show_Streaming = "0"; Show_Latency = "0"; Technology = "User Logic"; File_Count = "1"; Port_Count = "24"; Component_Desc = "ISP1362"; Module_Name = "ISP1362_IF"; } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "2"; Data_Width = "16"; Has_IRQ = "1"; Base_Address = "0x00900080"; Has_Base_Address = "1"; Read_Wait_States = "100ns"; Write_Wait_States = "100ns"; Setup_Time = "200ns"; Hold_Time = "200ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "4"; } Address_Group = "0"; } PORT_WIRING { PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iADDR { width = "2"; direction = "input"; type = "address"; } PORT iRD_N { width = "1"; direction = "input"; type = "read_n"; } PORT iWR_N { width = "1"; direction = "input"; type = "write_n"; } PORT iCS_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT OTG_DATA { width = "16"; direction = "inout"; type = "export"; } PORT OTG_ADDR { width = "2"; direction = "output"; type = "export"; } PORT OTG_RD_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_WR_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_CS_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_RST_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_INT0 { width = "1"; direction = "input"; type = "export"; } PORT OTG_INT1 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DREQ0 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DREQ1 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DACK0_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_DACK1_N { width = "1"; direction = "output"; type = "export"; } PORT oINT { width = "1"; direction = "output"; type = "irq_n"; } PORT iFSPEED { width = "1"; direction = "input"; type = "export"; } PORT iLSPEED { width = "1"; direction = "input"; type = "export"; } PORT OTG_FSPEED { width = "1"; direction = "output"; type = "export"; } PORT OTG_LSPEED { width = "1"; direction = "output"; type = "export"; } } } MASTER avalonM { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Data_Width = "32"; Address_Width = "8"; Max_Address_Width = "32"; Is_Enabled = "0"; } PORT_WIRING { } } SLAVE ahbS { SYSTEM_BUILDER_INFO { Bus_Type = "AHB"; Has_IRQ = "0"; Has_Base_Address = "1"; Address_Width = "10"; Data_Width = "32"; Base_Address = "--unknown--"; Address_Alignment = "native"; Read_Wait_States = "0"; Write_Wait_States = "0"; Is_Enabled = "0"; } PORT_WIRING { } } MASTER ahbM { SYSTEM_BUILDER_INFO { Bus_Type = "AHB"; Address_Width = "32"; Max_Address_Width = "32"; Data_Width = "32"; Interrupts_Enabled = "1"; Irq_Scheme = "Individual_requests"; Is_Enabled = "0"; } PORT_WIRING { } } HDL_INFO { Imported_HDL_Files = "./ISP1362_IF.v"; Synthesis_HDL_Files = "./ISP1362_IF.v,__PROJECT_DIRECTORY__/ISP1362.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments IMPORTED_WAIT 0 NIOS_GEN_WAITS 1 SIMULATE_IMPORTED_HDL 1 PORT_TYPE "Avalon Slave" HDL_IMPORT 1 TIMING_UNITS "ns" UNIT_MULTIPLIER 1 SETUP_VALUE 200 HOLD_VALUE 200 WAIT_VALUE 100 ADDRESS_WIDTH 32 MODULE_LIST "" SHOW_STREAMING 0 SHOW_LATENCY 0 TECHNOLOGY "User Logic" FILE_COUNT 1 PORT_COUNT 24 COMPONENT_DESC "ISP1362" MODULE_NAME "ISP1362_IF"

---

DM9000A

user_logic_DM9000A_classic v2.0

Parameters instancePTF MODULE DM9000A { class = "user_logic_DM9000A"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "1"; Data_Width = "16"; Has_IRQ = "1"; Has_Base_Address = "1"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "8"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00900090"; Address_Group = "0"; } PORT_WIRING { PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iCMD { width = "1"; direction = "input"; type = "address"; } PORT iRD_N { width = "1"; direction = "input"; type = "read_n"; } PORT iWR_N { width = "1"; direction = "input"; type = "write_n"; } PORT iCS_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT oINT { width = "1"; direction = "output"; type = "irq"; } PORT ENET_DATA { width = "16"; direction = "inout"; type = "export"; } PORT ENET_CMD { width = "1"; direction = "output"; type = "export"; } PORT ENET_RD_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_WR_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_CS_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_RST_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_INT { width = "1"; direction = "input"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "iDATA"; radix = "hexadecimal"; } SIGNAL b { name = "oDATA"; radix = "hexadecimal"; } SIGNAL c { name = "iCMD"; } SIGNAL d { name = "iRD_N"; } SIGNAL e { name = "iWR_N"; } SIGNAL f { name = "iCS_N"; } SIGNAL g { name = "iRST_N"; } SIGNAL h { name = "oINT"; } SIGNAL i { name = "ENET_DATA"; radix = "hexadecimal"; } SIGNAL j { name = "ENET_CMD"; } SIGNAL k { name = "ENET_RD_N"; } SIGNAL l { name = "ENET_WR_N"; } SIGNAL m { name = "ENET_CS_N"; } SIGNAL n { name = "ENET_RST_N"; } SIGNAL o { name = "ENET_INT"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/DM9000A_IF.v, __PROJECT_DIRECTORY__/DM9000A.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

ps2_0

altera_up_avalon_ps2_classic v6.1

Parameters instancePTF MODULE ps2_0 { class = "altera_up_avalon_ps2"; class_version = "6.1"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Default_Module_Name = "ps2"; Top_Level_Ports_Are_Enumerated = "1"; Is_Enabled = "1"; Clock_Source = "clk"; View { MESSAGES { } } } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT clk { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT reset { width = "1"; width_expression = ""; direction = "input"; type = "reset"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { } } SIMULATION { DISPLAY { } } SLAVE avalon_PS2_slave { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "1"; Address_Alignment = "dynamic"; Data_Width = "32"; Has_Base_Address = "1"; Has_IRQ = "1"; Setup_Time = "0"; Hold_Time = "0"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; Read_Latency = "1"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "0"; Is_Readable = "1"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "0"; Read_Wait_Value = "1"; Write_Wait_Value = "1"; Hold_Value = "0"; Timing_Units = "cycles"; Read_Latency_Value = "1"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "dynamic"; Is_Printable_Device = "0"; interface_name = "Avalon Slave"; external_wait = "1"; Is_Memory_Device = "1"; } } PORT_WIRING { PORT address { width = "1"; width_expression = ""; direction = "input"; type = "address"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT chipselect { width = "1"; width_expression = ""; direction = "input"; type = "chipselect"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT byteenable { width = "4"; width_expression = ""; direction = "input"; type = "byteenable"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT read { width = "1"; width_expression = ""; direction = "input"; type = "read"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT write { width = "1"; width_expression = ""; direction = "input"; type = "write"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT writedata { width = "32"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT PS2_CLK { width = "1"; width_expression = ""; direction = "inout"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT PS2_DAT { width = "1"; width_expression = ""; direction = "inout"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT irq { width = "1"; width_expression = ""; direction = "output"; type = "irq"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT readdata { width = "32"; width_expression = ""; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT waitrequest { width = "1"; width_expression = ""; direction = "output"; type = "waitrequest"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Altera_UP_Avalon_PS2.v,__PROJECT_DIRECTORY__/Altera_UP_PS2.v,__PROJECT_DIRECTORY__/Altera_UP_PS2_Command_Out.v,__PROJECT_DIRECTORY__/Altera_UP_PS2_Data_In.v, __PROJECT_DIRECTORY__/ps2_0.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

binary_vga_controller_0

binary_vga_controller v1.0

Parameters instancePTF MODULE binary_vga_controller_0 { class = "binary_vga_controller"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Top_Level_Ports_Are_Enumerated = "1"; Is_Enabled = "1"; Clock_Source = "clk"; View { MESSAGES { } } } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT iCLK { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { ram_size = "19'b1001011000000000000"; } } SIMULATION { DISPLAY { } } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "19"; Address_Alignment = "native"; Data_Width = "16"; Has_Base_Address = "1"; Has_IRQ = "0"; Setup_Time = "1cycles"; Hold_Time = "1cycles"; Read_Wait_States = "0cycles"; Write_Wait_States = "0cycles"; Read_Latency = "0"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "0"; Is_Readable = "1"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "1"; Read_Wait_Value = "0"; Write_Wait_Value = "0"; Hold_Value = "1"; Timing_Units = "cycles"; Read_Latency_Value = "0"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "native"; Is_Printable_Device = "0"; Interleave_Bursts = "0"; interface_name = "Avalon Slave"; external_wait = "0"; Is_Memory_Device = "0"; } } PORT_WIRING { PORT oDATA { width = "16"; width_expression = ""; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iDATA { width = "16"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iADDR { width = "19"; width_expression = ""; direction = "input"; type = "address"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iWR { width = "1"; width_expression = ""; direction = "input"; type = "write"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iRD { width = "1"; width_expression = ""; direction = "input"; type = "read"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iCS { width = "1"; width_expression = ""; direction = "input"; type = "chipselect"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iRST_N { width = "1"; width_expression = ""; direction = "input"; type = "reset_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_R { width = "10"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_G { width = "10"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_B { width = "10"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_HS { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_VS { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_SYNC { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_BLANK { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT VGA_CLK { width = "1"; width_expression = ""; direction = "output"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT iCLK_25 { width = "1"; width_expression = ""; direction = "input"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Img_DATA.hex,__PROJECT_DIRECTORY__/VGA_Param.h,__PROJECT_DIRECTORY__/Img_RAM.v,__PROJECT_DIRECTORY__/VGA_Controller.v,__PROJECT_DIRECTORY__/VGA_NIOS_CTRL.v,__PROJECT_DIRECTORY__/VGA_OSD_RAM.v, __PROJECT_DIRECTORY__/binary_vga_controller_0.v"; } } sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)