The API allows an easy and standardized access to logic level circuit descriptions. The write part of the API can be used by benchmark providers to ensure a conforming storage of their circuits. The read API is useful for researchers and students to access these circuits in a uniform manner. For this purpose, routines for netlist access and traversal facilitate the application process.
The benchmarks are stored in a subset of the Verilog language. Combinational and synchronous sequential circuits are supported.
Currently we have most of the previous benchmark circuits converted into this format. We would like to encourage industrial companies as well as other institutions to provide benchmarks by using this standard format.
If you have any questions, please contact Andreas Kuehlmann (kuehl@cadence.com).