List of Contents

1. Introduction
2. Background
3. Video Client Model
4. Simulation Environment & Jitter Modeling
5. Feedback Mechanism: Phase-Locked Loop
6. Results
7. Conclusion
8. Acknowledgement
9. Downloading Simulation Kit
10. References

Introduction

Due to network jitters, the packets suffer a stochastic delay during transport over the packet network and arrive at their destination with stochastic interarrival times. Hence, at the receiver side it is necessary to recover the clock frequency of the data source. Realizing that there is no timing information provided in AAL5, we need to implement a clock recovery mechanism consisting of a elastic buffer and a feedback loop. The basic idea of this feedback control, or namely Phase-Locked Loop(PLL), has been studied for years in analog and digital circiuts that receives analog signals and bit streams respectively. In this paper, possible approaches to the synchronization recovery mechanism will be studied and simulated for a software decoder in the client side of a VoD system. These differ from classical PLL's feedback mechanism as it locks on packets instead of bits.





Background

The following figure shows the general architecture of VoD service over the ATM network and Internet. In the case of ATM network the MPEG-2 Systems Layer is mapped onto the AAL5, and the TS stream format is supported for CBR/VBR transmission.


Figure 1 General architecture of VoD service over networks

The ATM Adaptation Layer5(AAL5) has 48 bytes of payload in the SAR-PDU, but 8 bytes trailer at the end of the CPCS-SDU or CPCS-PDU payload (188 bytes of 1 MPEG-2 TS packet). Therefore, 5 ATM cells are needed for 1 MPEG-2 TS packet and the last cell will be partially filled. Another alternative would be to transport 2 MPEG-2 TS packets in 8 completely filled ATM cells. This is actually the default size that all equipment shall support in order to ensure a base level of interoperability[10]. AAL5 provides CRC-32, but there is no provision for timing recovery mechanism [11].

In the ATM Forum's specification for Video on Demand there is no SSCS: the MPEG-2 Layer(Transport Stream) is mapped directly onto the AAL Layer(AAL5).

For the receiver to recover the system time clock information correctly, the interarrival times of the Program Clock References(PCR) at the MPEG-2 decoder must match the interarrval times of the PCRs entering the AAL5 at the source; otherwise, the receiver needs to compensate for the induced PCR packetization and network jitter before delivering the bit stream to the decoder[10]. The ATM Forum VoD Spec. requires the receiver to remove the inherent PCR packetization jitter of 1 TS packet, caused by allowing the PCR to occur in any Transport Packet within the AAL5-SDU.





Video Client Model

Figure 1 below shows a diagram of the video client model in a VoD system [8]. It consists of four sections, namely reception, demultiplexing, decoding, and presentation.


Figure 2 Video Client Model[8]

The reception section receives AAL5 PDU(Protocol Data Unit)s from the network. The size of the network interface is of several PDUs. In some digital set-top-boxes the size is only 376 bytes to minimize cost (8 ATM cells using AAL5). This size prevents the server from sending larger PDUs[8]. A smoothing buffer follows after the network interface, whose mission is to supress the jitter introduced in the network. The PLL driven by the smoothing buffer occupancy is to remove the jitters accumulated in the server and network and caused by the independent clocks used in the server and the client. The output of the smoothing buffer is a MPEG-2 TS(Transport Stream) which is demultiplexed and decoded in the following sections. The presentation section plays the final output from the whole system, and this is where the subjective QoS measurements are taken. This Video Client Model is controlled by the two subsystems, namely the PLL and the Timebase Recovery system. The Timbase Recovery system generates different levels of synchronization from the PLL signal and the timestamp inside the incoming video stream. The duty of the Error Concealment system is to take appropriate actions in the case of error conditions(i.e. buffer overflow, underflow, etc). Some parameters of this model can be scaled depending on the type of video client model used. Memory constraints in digital set-top-boxes can be avoided in software-based implementation[8].





Simulation Environment and Jitter Modeling

As the starting point of the synchronization recovery a G/D/1/n (generic arrival, deterministic service, single server, and size n buffer) queueing system was designed and implemented to simulate the PLL feedback mechanism. The generic arrival usually represents a slotted system like the ATM network; hence, the Gamma distribution function was used to generate random numbers which corresponds to the interarrival times of the incoming PDUs in the real world. The deterministic service time associates to the server(demux and decoder) in the client or receiver side. After the feedback mechanism enters its stable mode or the PLL gets locked, this service time is no longer a constant and is to be changed with respect to the PLL's output signal which corresponds to the actual frequency of the transmitter.

In order to allow an initial adjustment of the receiver clock, the following assumptions were made.

• An absolute frequency measurement of the transmitter clock is performed with a very stable oscillator and is sent to the receiver as a control packet.
• At the receiver side, this remote measured frequency is reconstructed in the initial stage as the PLL's free-running frequency; hence, the system will deviate minimally from the original measured frequency. However, due to factors such as frequecy measurement error or the limited accuracy of the oscillator this reconstruction is imperfect, and therefore a dedicated feedback mechanism is added as will be described below.
• The measurement period is short enough as compared to the time needed for the packet FIFO filling level to increase or decrease by one due to a difference in the transmitter and the receiver clock.

As mentioned above, for generating jittered interarrival times the gamma distribution function was used. One important assumption made for the simulation is that the maximum amplitude of the jitter on the packet interarrival times must be smaller than half the mean sending period(this condition excludes networks where packets arrive out of sequence). If this condition is not satisfied, the jittered interarrival times will be distributed from zero over a wide range which causes the situation that the PLL is impossible to acquire its lock mode.

In general the jitter is considered as a part of delay. The delay experimented by the N th packet consists of a fixed constant delay(caused by propagation, transmission, and switching) and a jitter which is variable and can be modeled as a random variable[7]. The probability distribution of the fixed and variable components of delay is ploted in the figure below.


Figure 3 Fixed and variable components of delay
To simulate the variable delay or jitter part under the assumption made above, we need to scale the ordinary gamma function by the scale factor of 0.5. The distribution of the actual interarrival times generated and used in this simulation is plotted in Figure 4. For this plot 100,000 arrivals, mean interarrival time of 1.0, the scale factor of 0.5, and various shape parameters(alpha) were used. As shown, if alpha is equal to 1, then it is the same as the exponential arrival.

Figure 4 Distribution of interarrival times used in simulation




Feedback mechanism: Phase-Locked Loop

Figure 5 shows the basic PLL diagram. One of the most intriguing capabilities of PLL is its ability to suppress noise superimposed on its input signal. Even if the input signal is buried in noise, almost no noise will be noticeable in the output of the loop filter(with low enough corner frequency), and the DCO will operate in such a way that the phase of the PLL's output signal is equal to the average phase of the input signal. As we know, the noise at the input causes the zero crossing(for sinusoidal signals) to be advanced or delayed in a stochastic manner, and this can be seen as same as the network jitter imposed on the incoming PDUs.


Figure 5 The PLL diagram

The PLL's mission is to track the actual frequency of the incoming PDUs. It should be noted that since we are dealing with the simulation which can mainly be used for the software implementation of PLL, all the variables were chosen in the software point of view in order to relate the PLL theory to the study of synchronization recovery in a VoD system. In other words, the major restriction that applies to the implementation of Software PLL is the execution period to be short enough as compared to the time needed for each PDU's arrival. Each component in the PLL diagram was designed and implemented as the following:




Phase Detector

The implemented PLL is driven by the interarrival times between incoming PDUs. The Phase Detector first detects the phase error by taking the difference between the interarrival times of the incoming PDUs and the output signal of the PLL, which is relevant to the interarrival time, generated from the Digitally Controlled Oscillator. If we assume that the input signal and the PLL's output signal are the same at the initial state, whenever there is a change in the frequency of the input signal, the Phase Detector generates a phase error: it simply means that if there is no phase error, then the frequencies are the same, and the PLL is said to be locked.




Phase Error Averager

The phase error is sent to the phase error averager of size N, which can be seen as a FIFO buffer. This averaging reduces phase change steps by a factor of approximately N compared to no averaging. As a result, the phase error envelope is also reduced; however, it increases the error pull-in transients because the loop response is slower. The averaging also ensures that frequency step changes are about the same as without PCR discontinuities(at intervals shorter than the loop time constants). In this simulation the maximum averager size that could be used to acquire the lock mode was 4. When the size was greater than 4, then the PLL was not able to acquire a lock mode, and the phase error increased linearly with the oscillating behavior. This is due to the fact that a phase error at an instance is not reflected at the output of the averager at the same instance, and this causes the PLL to be out-of-lock. The maximum allowable size of the averager was found to be implementation specific.




Digital Loop Filter(2nd order)

The averaged phase error is then sent to the digital loop filter. For a PLL there exists almost always a difference between the incoming PDUs' frequency and the free-running frequency of DCO(in this case the referece clock initially received). This difference may be due to an actual difference between the transmitter and receiver clock or it may be due to a Doppler shift [3]. Therefore a 2nd order filter was chosen, which contains an integrator being capable of compensating this difference in such a way that no steady-state phase error remains. The architecture of the common 2nd order filter chosen for the simulation is shown in Figure 4.


Figure 6 The 2nd order loop filter
The digital equivalent of the analog integrating element such as a RC filter is a digital accumulator. As shown in the figure above the accumulator is simply mechanized using an adder and a unit delay connected. Due to the presence of the accumulator(or integrator) the impulse response of the system is IIR. This filter can be formulated as the following:



From the last equation we can see that the Z-transform digital filter response has a pole at z = 1 and a zero at z = G₁ / (G₁ + G₂). This means that the pole is on the unit circle and the input to the filter is right-sided sequence(n > 0). Since the ROC of the filter in the z-plane will be the outside the unit circle, excluding the circle, the filter response is unstable. In order to have the filter response stable, we must have the pole inside the unit circle since the ROC must not contain any pole. Because of this, the Z-transform filter response was slightly modified in order to have the pole inside the unit circle and to make it possible for actual hardware implementation as



When chossing G₁ and G₂ it is necessary to consider the fact that what we would like to keep is the dc component and that the high frequency components should be suppressed. This corresponds to w = 0 or having the magnitude of the frequency to be 1; therefore, by setting z^-1 = 1, we can choose G₁ and G₂ from the equation below. For this simulation G₁ = 0.1 and G₂ = 0.09 were used.



It should be noted that the values of G₁ and G₂ do not affect the main characteristic of the PLL, but change the pull-in transient, the frequency excursion, or the length of the overshoot. The various plots for the loop filter fresponse are shown in the figure below.

Figure 7 Frequency response of the loop filter



Digitally Controlled Oscillator(DCO)

The static phase error from the loop filter enters the DCO. The Z-transform representation of the DCO is



As above the output of the DCO is the reconstructed phase which is the summation of the previous phase and the previous phase error. This phase is fed back into the phase detector to track the phase of the incoming PDUs.





Results

The following figures show the PLL's tracking action.


Figure 8.1 Frequency response of PLL with no presence of jitter
When there is no jitter presented as in Figure 8.1, from the initial frequency offset, in this case 50 ppm, the PLL tracks the actual frequency of the sender. The simulation is based on the arrivals of PDUs whose size is 376 bytes for each SDU(contains 2 TS packets) plus 8 bytes of trailer. Hence, from the ATM layer, in order to re-assemble a PDU 8 ATM cells are needed. This makes us possible to calculate the nominal PDU interval(i.e. sender rate = 1 Mbps, nominal PDU interval = 0.003392 sec). Since we are not dealing with any jitter in this case, but with constant error, the PLL linearly tracks the incoming PDUs frequency and then finally gets into the lock range(or tracking mode).

When the jitter is introduced in the network, the incoming PDUs' interarrival time fluctuates minimally from the initial clock frequency of the transmitter received as a control packet at the beginning. This frequency is set as the free-running frequency of the PLL in the initial stage. Again, with small deviations the PLL acquires its lock mode as shown below (the shape parameter alpha for gamma distribution was set to 2).


Figure 8.2 Frequency response of PLL with presence of jitter
In order to track the actual frequency of the transmitter, the PLL starts tracking the incoming stream's phase or frequency. From the pull-in transient or the time for the PLL to get into the tracking mode, we can determine the size of the smoothing buffer in the network interface. As soon as the PLL gets locked, we can use the signal information from the PLL to control the buffer occupancy in the Timebase recovery system as shown in Figure 3.

For both Figure 8.1 and 8.2 no error averager was used. The following figure shows the case when the size of the averager is 3.


Figure 8.3 Frequency response of PLL with averager size = 3
Comparing to Figure 3 it is shown that it takes longer for the PLL to acquire the lock mode, but requires small frequency step size after acquiring the lock modecomparing to Figure 3.

When the PLL is tracking the frequency of the incoming PDUs, the phase error also deviates as the frequency error. This is plotted in Figure 8.4 for initial phase offset of 1.0 usec.


Figure 8.4 Phase response of PLL with presence of jitter
In this paper the N th phase error was defined as the difference between the N th PDU's actual arrival time(not interarrival time) and the N th reconstructed DCO output's generation time(the frequency error was obtained from each actual interarrival time and the corresponding DCO output). As the PLL tracks the input, the phase error also gets into the satble mode,but is not necessarily to be zero. However, there is no need to make the N th actual arrival time and the N th DCO output time in phase because as long as the phase error becomes we can simply shift the DCO output by the amount less than the mean interarrival time. For this reason the phase error was found to be less important than the frequency error for analyzing the PLL's performance.

Once the PLL is locked, the output of the PLL is fed into the Timebase recovery system which drives the demux and decoders as described before in Figure 3.





Conclusion

In this paper, a possible feedback mechanism using software PLL was simulated for incoming PDUs with jitter. The result is encouraging. As seen above the PLL's tracking action showed that after a certain period of time, depending on the variance on jitter, the PLL eventually track the actual frequency of the transmitter, under the assumptions made previously. This algorithm can be apllied to most of packet networks with no timing provision at the client side.





Acknowledgement

The author would like to thank Javier Zamora and Jae-Beom Lee for their guidance and valuable suggestions.





Downloading Simulation Kit

You can download the simulation kit with PLL for educational purpose. This kit can be used to simulate jitter and PLL analysis with G/D/1/n queueing system driven by interarrival times of PDUs. All codes are heavily commented, and simple to follow. The C/C++ codes perform the actual simulation, and the m files are to be used in Matlab 4.2c in order to view and analyze the outputs. This m file, PLLchecker.m, creates an easy to use GUI for analyzing both frequency and phase errors generated during the simulation run time. The C++ codes are tested on SGI IRIX 5.3. In order to run the m file you need to set the path to the file before executing in Matlab 4.2c(i.e. >>path(path,'/homes/mjp/project/src') ). For further information about the input parameters and calculation used during the simulation, please refer to README file in "src" directory.

In order to download sync.tar.gz (1.78M), the complete software, for the simulation, please send an e-mail to the author at mjp@ctr.columbia.edu for permission to use.





References

[1] Roland E. Best, Phase-Locked Loops , McGraw-Hill, 2Ed, 1993

[2] W. C. Lindsey, C. M. Chie, " A survey of Digital Phased-Locked Loops, " Processings of the IEEE, Vol. 69, No. 4, April 1981

[3] C. E. Holborow, " Simulation of Phase-Locked Loop for processing jittered PCRs, " ISO/IEC JTC1/SC29/WG11, MPEG94/071, March 1994

[4] H. Meyr, G. Ascheid, Synchronization in Digital Communications , Wiley series in Telecommunications, Vol.1, 1990

[5] M. E. Nilson, " Clock recovery using jittered timestamps, " ISO-IEC/JTC 1/SC29/WG11, MPEG94/145, March 1994

[6] M. D. Prycker, M. Ryckebusch, P. Barri, " Terminal syncronization in asynchronous networks, " ICC '87 Seattle, June 1987

[7] Javier Zamora, " Issues of Videoservices over ATM, " CTR Technical Report No. 405-95-11, Center for Telecommunications Research, Columbia University, New York, May 1995

[8] Javier Zamora, Stephen Jacobs, Alexandros Eleftheriadis, Shih-Fu Chang and Dimitris Anastassiou, " A Practical Methodology for Guaranteeing QoS for Video on Demand, " CTR Technical Report No. TR-447-96-13, Center for Telecommunications Research, Columbia University, New York, 1996

[9] ATM_Forum/af-saa-0049.001 " Audiovisual Multimedia Services: Video on Demand Specification 1.1, " 1996

[10] ATM_Forum/96-1575 " Audiovisual Multimedia Services: VBR MPEG-2 Specification, " 1996

[11] ITU-T Recommendation I.363, " B-ISDN ATM Adaptation Layer(AAL) Specification, " March 1993

[12] Xavier G. Adanez, Adrea Basso, Jean-Pierre Hubaux "Study of AAL5 and a New AAL Segmentation Mechanism for MPEG-2 Video over ATM," TCOM Laboratory, Telecommunication Group, Swiss Federal Institute of Technology, 1996