CSEE W3827 - Fundamentals of Computer Systems

Call number 22152

[Course Info][Assignments] [Discussion Board (via Courseworks)][Grading Info]

Course Information (Also available in pdf)

Professor Dan Rubenstein
Fall 2008


Contact Information
Who Office Phone E-mail Office Hours
Prof. Dan Rubenstein CEPSR 816 (212) 854-0050 danr@cs.columbia.edu Tu 10:30-11:30am, Th 2-3pm or by appt
TA Abhinandan Majumdar Mudd 122A N/A am2993@columbia.edu M,W 12:00pm-1:00pm
Date   #   Topics/chapters covered   Reading   Assigned   Due  
9/3   1   Intro; Overview of Computer Architecture; Definitions (bit,byte,word)   M&K Ch 1      
9/8   2   Binary number representations: 2's complement; 1's complement; floating point representations: overflow and underflow   M&K 4.3-4.4, 10.7, P&H 3.6 skip FP in MIPS   HW #1    
9/10   3   Logic gates; XOR; Boolean Algebra; NAND and NOR gates; Taking complements; DeMorgan's Theorem; Duals   M&K 2.1-2.2, 2.8, 2.9      
9/15   4   Standard Forms: minterms, maxterms, sum-of-products, product-of-sums   M&K 2.3   HW #2   HW #1  
9/17   5   K-maps: simplification with implicants, Don't-care conditions   M&K 2.4-2.5      
9/22   6   *** Catchup ***     HW #3   HW #2  
9/24   7   Combinatorial Circuit Design: Multi-bit output functions; standard combinatorial circuits (enabler, decoder, encoder, priority encoder, mux   M&K 3.1, 3.3, 3, 3.6-3.9      
9/29   8   Arithmetic funcs: Adder (half, full, ripple-carry, adder-subtractor); Contraction; Shifter   M&K 4.1-4.2, 4.5, 9.4   HW #4   HW #3  
10/1   9   Sequential Circuitry: Latch, Flip-Flops, timing issues   M&K 5.1-5.3, 5.6      
10/6   10   Sequential Circuit Analysis & Design: State machines   M&K 5.4-5.5   HW #5   HW #4  
10/8   11   PLAs; ROM; Register Design: Load and Transfer   M&K 6.8, 7.1-7.3      
10/13   12   Register Design cont'd: MicroOps and Counters, mux and serial transfer   M&K 7.5-7.6, 7.8-7.9     HW #5  
10/15   13   *** Catchup and/or Midterm review ***        
10/20   14   MIDTERM (in class)        
10/22   15   Memory Design   M&K 8.1-8.7      
10/27   16   Processor Design: Datapath, ALU   M&K 9.1-9.5   HW #6    
10/29   17   Control Word; Simple Arch; Instruction Decoder   M&K 9.6-9.8      
11/3   --   ELECTION DAY - NO CLASS!        
11/5   18   Instruction Types and Formats   P&H 2.1-2.5   HW #7   HW #6  
11/10   19   Branches, stacks, heaps, immediate addressing   P&H 2.6-2.7, 2.9      
11/12   20   Single Cycle Datapath   P&H 5.1-5.4   HW #8   HW #7  
11/17   21   Single Cycle Datapath cont'd        
11/19   22   Multi-Cycle Datapath   P&H 5.5   HW #9   HW #8  
11/24   23   Pipelining   P&H 6.1-6.8      
11/26   24   Cache & Cache Replacement Policies   P&H 7.1-7.2   HW #10   HW #9  
12/1   25   *** Catchup and/or review ***        
12/3   26   *** Catchup and/or review ***       HW #10  
12/8   27   *** Catchup and/or review ***        
12/17 @ 1:10pm??     FINAL EXAM: Location TBD        

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