CSEE E6861y: Handouts



Handout #1

Course Information ( PDF )

Handout #2

Syllabus ( PDF )

Handout #3

Homework, Project and Exam Schedule ( PDF )

Handout #4

Questionnaire ( PDF )

Handout #5

The Quine-McCluskey Method ( PDF )

Lecture #1: Slides ( PDF )

Handout #6

Multi-Output Functions (hardcopy only)*

Handout #7

Heuristic Minimization of Two-Level Circuits (hardcopy only)*

Handout #8

Rick Rudell's PhD Thesis: Chapters 1 and 2 ( PDF )

Handout #9

Homework #1 (PDF )

Handout #9a

Homework #1, Problem #1 (TXT ) (Getting Started with SIS )

Lecture #2 (part 1): Slides ( PDF )

Lecture #2 (part 2): Slides ( PDF )

Handout #10

Heuristic Two-Level Logic Minimization (hardcopy only)*

Handout #11

Overview of Tautology Checking (PDF )

Handout #12

Handout of Examples (PDF )

Lecture #3: Slides ( PDF )

Handout #13

Homework #2 (PDF )

Handout #14

Homework #1 Solutions (hardcopy only)*

Handout #15

Hachtel/Somenzi ch. 5.8 (problems) (hardcopy only)*

Handout #16

Overview of Fast Complementation (PDF )

Handout #17

Rudell's Master's thesis (UC Berkeley): chs. 4.7-4.8 Last-gasp, super-gasp, make-sparse (PDF )

Handout #18

Homework #3 (PDF )

Lecture #6 (part 1): Slides ( PDF )

Lecture #6 (part 2): Slides ( PDF )

Handout #19

Homework #2 Solutions (hardcopy only)*

Handout #20

Kernels, Co-Kernels and Extraction Examples (PDF )

Handout #21, #21(a-e)

#21 Midterm Homework and CAD Mini-Project ( PDF )

#21a Midterm CAD Mini-Project: Designing a Tool for Prime Generation and Essentials ( TXT )

#21b Introduction to the SIS CAD Package: Multi-Level Logic Optimization ( TXT )

#21c Frequently-Asked Questions (FAQ) *(Updated Regularly -- Refresh Your Browser)* ( TXT )

#21d Sample Examples and Solutions (from David Jew) ( ZIP )

#21e CAD Mini-Project: Writeup, Submission and Demo Information ( TXT )

Handout #22

Overview of Fast Prime Generation (PDF )

Handout #23

Prime Generation Problem Example (PDF )

Handout #24

Basic Tree-Based Covering Example (area-oriented) (PDF )

Handout #25

Homework #3 Solutions (hardcopy only)*

Handout #26

Delay-Oriented Technology Mapping Handout (PDF )

Handout #27

"Technology Mapping for Low Power",
V. Tiwari, P. Ashar and S. Malik,
Proceedings of ACM/IEEE Design Automation Conference (1993) (PDF )

Handout #27a

Errata and Clarifications: Tiwari et al. paper (#27) (TXT )

Handout #28

Homework #4 ( corrected) (PDF )

Handout #29

"A Procedure for Placement of Standard-Cell VLSI Circuits",
A.E. Dunlop and B.W. Kernighan,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Jan. 1985) (PDF )

Handout #30

Kernighan-Lin partitioning example (courtesy of Prof. David Pan, UT Austin) (PDF )

Handout #31

Midterm CAD Problem (written, SIS) Solutions (hardcopy only)*

Handout #32

Retiming Synchronous Circuitry (C.E. Leiserson/J.B. Saxe, Digital SRC Tech report, Aug. 1986) ( PDF)

Handout #33, #33(a-d)

#33 Final Homework and CAD Mini-Project ( PDF )

#33a Introduction to the SIS CAD Package: Technology Mapping ( TXT )

#33b Final CAD Mini-Project: Designing a Retiming Tool ( TXT )

#33c Final CAD Mini-Project: Details on Input/Output File Format ( TXT )

#33d Final CAD Mini-Project: Correlator Example ( TXT )

#33e Checkpoint Information ( TXT )

#33f Final CAD Mini-Project: Alternative Example: More Complex Correlator ( TXT )

#33g Frequently-Asked Questions (FAQ) *(Updated Regularly -- Refresh Your Browser)* ( TXT )

#33h Final Demo Information ( TXT )

#34i Final Report and Submission Information ( TXT )

Handout #34

"An Introduction to High-Level Synthesis",
P. Coussy, D.D. Gajski, M. Meredith and A. Takach,
IEEE Design and Test of Computers (July/Aug. 2009) (PDF )

Handout #35

Homework #4 Solutions (hardcopy only)*

Handout #36

Resource Sharing Handout (hardcopy only)*

Handout #37

Scheduling Handout (hardcopy only)*

Handout #38

BDD Chapter (hardcopy only)*

Handout #39 OBDD Handout ( PDF )

Handout #40

Homework #5 (PDF )

Handout #41

Homework #5 Solutions (hardcopy only)*


*Hardcopy only; see TA for copies.