Date assigned

Assigned Readings

Sept. 8

• B/V: Preface, ch. 1, ch. 2.9, ch. 4.11

Sept. 8 (optional)

Review/Background Reading:

• basics of combinational logic: B/V ch. 2.1-2.8, 2.11-2.12
• implementation technology: B/V ch. 3.1-3.5
• combinational logic synthesis: B/V ch. 4.1-4.8, 4.13-4.14
• Additionally, the Roth book (see Handout #1) is a good self-study guide and refresher resource for basic digital logic; it will be on reserve in the Monell Engineering Library.

Sept. 10

• Handout #5 Quine-McCluskey Method
• B/V: ch. 7.11

Sept. 10 (optional)

Review/Background Reading:

• latches, flipflops, basic registers: B/V ch. 7: introduction + ch. 7.1-7.9

Sept. 15

• B/V: ch. 7.15-7.17
• B/V: ch. 8: intro. + 8.1
• (optional, on reserve): LFSR's: Wakerly book (ch. 8.5.8)
• (optional, on reserve): basic counter design: Sunggu Lee, "Design of Computers and Other Complex Digital Devices" (pp. 62-65)

Sept. 15 (optional)

Review/Background Reading:

• B/V ch. 4.14
• B/V ch. 6: intro. + ch. 6.1-6.4

Sept. 17

• B/V: ch. 8.2-8.3
• B/V: ch. 8.5 (except 8.5.3)
• B/V: ch. 8.7 (note: B/V's "counter" is actually an FSM!)

Sept. 22

• B/V ch. 2.10 Introduction to VHDL
• B/V ch. 4.12 VHDL basic circuit examples
• arithmetic circuits: ch. 5.5: intro + 5.5.1-5.5.3

Sept. 24

• B/V ch. 5 intro. + 5.1-5.3, ch. 5.8
• VHDL for comb. circuits: B/V ch. 6.6: intro + 6.6.1-6.6.2

Sept. 24 (optional)

VHDL Reading/Reference:

• Bhasker ch. 2, Wakerly VHDL section

Sept. 29

• arithmetic circuits: B/V ch. 5.5.4
• VHDL for comb. circuits: B/V ch. 6.6.3-6.6.5, 6.6.8 (NOTE: skip sequential statements for now!)
• conclusion/solved problems: B/V ch. 6.7-6.8

Sept. 29 (optional)

Recommended VHDL Reading:

• B/V Appendix A.1-A.7, A.11-A.12

Oct. 1

• Handout #7: Iterative Circuits

Oct. 6

• B/V: ch. 8.6 intro. + 8.6.1, ch. 8.9
• Handout #10: ch. 9.5
• Handout #11: ch. 5.2.1, 5.2.3 (skip 5.2.2 for now)
• Handout #12: ch. 5.1 (skip rest for now)

Oct. 8

• CLA's: Handout #11: ch. 5.2.2
• CLA's and conditional sum adders: Handout #12: ch. 5.2-5.3

Oct. 13

• Handout #13 (all)
• Handout #14 (all)
• Handout #16, read carefully: pp. 1-17, pp. 26, pp. 44-47, rest: skim
• Handout #17, Prefix Adders, ch. 5.6

Oct. 15

• Handout #18 (all)
• B/V: sequential VHDL ('sequential'/'behavioral'/using 'process stmts.'): B/V ch. 6.6.6-6.6.7, ch. 7.12-7.13, ch. 8.4, 8.5.3
• B/V: ch. 5.6, ch. 5.9 p. 311

Oct. 20

• Handout #19 (all)

Oct. 22

• Handout #21: read abstract, sections I-II, III (but skip/skim subsections on optimality and implementation), section V.
• Handout #22: read abstract, sections 1-2, 6-7.

Oct. 27

• Handout #24: pp. 1-28, 45-53
• Handout #28: read all

Oct. 29

• Handout #25: read pp. 1-35 (skim/skip rest)
• Handout #26: read all

Nov. 10

• B/V ch. 8.10-8.13

Nov. 17

• Handout #33, ch. 8: intro., 8.1, 8.3
• Handout #34 (all)

Nov. 24

• Handout #40, read pp. 1-44, 51-55, 62, 67 (skim rest)