HANDOUT #39c:  MINI-PROJECT -- WHAT TO HAND IN

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	Required + Extra Credit Submission Information
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As indicated on Handout #39, you will pick only one of the two
RTL problems, and do a complete and optimized solution.

In particular, you will follow the first 7 steps of Handout #39. 
In addition I now ask you to do TWO ADDITIONAL REQUIRED STEPS:

    STEP #7a:  DISCUSS YOUR DESIGN EXPERIENCE

    STEP #7b:  TA PRESENTATION SESSION 

The remaining steps, Steps #8 and #9 (Handout #39) and #10 (demo),
are optional:  only if you do the extra credit part of the problem.

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WHAT TO HAND IN:  
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[NOTE:  most of the items below are listed on Handout #39, but in addition,
	I have now asked you to do STEPS #7a #7b.]


1. WRITTEN ALGORITHM (in PSEUDO-CODE) for the system's behavior.

	ADD 2-3 PARAGRAPHS OF TEXT DISCUSSION, explaining how your
	algorithm works, what decisions you made, what level of optimization
	you achieved (i.e. how many operations per clock cycle, in each
	iteration of the inner loop) and anything else
	that can help the TA understand the flow of its operation.

	This text should be clearly written, in a top-down way,
	that should document and clearly explain and give insight to an interested
	reader (e.g. the TA) the basics of your approach and specification.

2. WRITTEN FORMAL SPECIFICATION for the algorithm, in the form of 
	a GENERALIZED ASM (Moore style).

3. SHOW RESOURCE ALLOCATION OF DATAPATH COMPONENTS, i.e. select 
	datapath blocks needed (including any necessary MUXes, hardwiring 
	of inputs, and optimizations), following the written presentation
	style of Handout #34:  clearly drawing the block, indicating its
	operating truth table, indicating which states in the generalized
	ASM perform which operations on the component, etc.

4. IDENTIFY STATUS SIGNALS (outputs of datapath, which are inputs to 
	control), and allocate any additional datapath blocks required to 
	generate these status signals;

5. DRAW THE FINAL MICRO-ARCHITECTURE OF THE SYSTEM, showing all datapath 
	blocks, a single block for the control, and including all wiring 
	between blocks (external inputs/outputs, control and status signals);

6. DERIVE/DRAW A MOORE CONTROLLER ASM SPECIFICATION, using simple (B/V-style 
	control-only) ASM, following the technique presented in Handout #34;

7. GENERATE/DRAW THE CORRESPONDING MOORE STATE DIAGRAM for the controller 
	specification.

7a. DISCUSS DESIGN EXPERIENCE.  Write 3-4 paragraphs, explaining design 
	experiences, how you derived your solution, and challenges.
	Include discussion of how you dealt with the 'corner' cases
	(i.e. special cases, involving early termination, or requiring
	special handling like truncation, or anything else that
	required special handling).  Also indicate explicitly what
	level of optimization you achieved (# of core operations performed
	per clock cycle, in steady-state operation of the inner loop),
	and discussion of how you achieved this optimized level of
	performance.

7b. TA PRESENTATION SESSION.  Sign up for a 20 minute session with
        the TA.  Bring a copy of your completed solution writeup to the 
	Handout #39 RTL problem.  Be prepared to discuss, walking the 
	TA through your answers to #1-7a above, and to answer questions.

	See separate upcoming announcement for doodle signup.  Sign up with the
	same TA you met for the earlier checkpoint.  *All* group members
	must be present.  If you are doing extra credit, sign up 
	for a double session (two 20-minute sessions in succession).


8. OPTIONAL: EXTRA CREDIT ONLY. 
GENERATE A VHDL MODEL OF YOUR SYSTEM.  You are allowed to use structural 
modelling throughout, to get a nice hierarchical view. For individual 
components, you should use dataflow model for each combinational component, 
and when possible for each sequential datapath block. Use an appropriate 
top-level behavioral model (i.e. sequential) for the Moore state diagram. 
As usual, combinational blocks should be modelled using a dataflow style,
and sequential blocks using appropriate behavioral style (mixed with dataflow,
if needed).  

9. OPTIONAL: EXTRA CREDIT ONLY. 
SIMULATE YOUR VHDL MODEL, using the Altera tool environment, generating 
appropriate test vector sequences to thoroughly test the design, and hand 
in the result. You will also need to send the VHDL models and simulation 
results electronically to the TA.


10. OPTIONAL: EXTRA CREDIT ONLY.
DEMO WITH TA.  You will also need to set up a demo with the TA as part of 
step #7b above. See details below.


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WHERE/WHEN TO HAND IN:  
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required submission:
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For the required solution, parts #1-7 and #7a, put a hardcopy version
under Prof. Nowick's door by *4pm on MONDAY 12/12*.  (Just put under the
door, you don't need to hand it to him.)
 
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extra credit submission + demo:
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For the optional extra credit solution, also put HARDCOPY PRINTOUTS of parts #8-9
to Prof. Nowick at the same time:  by *4pm on MONDAY 12/12*.

Finally, send to Sumedh Attarde (sumedh256@gmail.com)
an ELECTRONIC ATTACHMENT of parts #8-9 *BEFORE 4pm on MONDAY 12/12* by email. 

Bring printouts of the electronic parts to your presentation/demo session.

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