Reining in Fabrication Cost with Brick and Mortar Chips

                    Martha Mercaldi Kim 
                 University of Washington

    Monday, March 10, 11AM, Interschool Lab, 7th Floor CEPSR


ABSTRACT:

Over the years Moore's Law has provided exponential growth in the raw
computational resources available to hardware architects.  At the same
time, however, chip fabrication costs have also skyrocketed, resulting
in expenses that relatively few institutions can afford.  As part of
my dissertation, I have proposed "brick and mortar" chips to mitigate
these high fabrication costs while offering the performance and
integration of a modern ASIC.  This work includes several
architectural design choices and innovations, including a polymorphic
on-chip network design.  I will demonstrate multiple modes of network
customization that this design allows, including topology and
buffering resources.  This single polymorphic network fabric can be
configured to mimic the topology and performance of optimally designed
application-specific networks with no appreciable overhead.  This
network is not only a critical enabler of brick and mortar-based
designs, but has broad applicability to any chip requiring an on-chip
network.  When used with brick and mortar, however, low-cost,
high-performance custom chips can become a reality.

BIO:

Martha Mercaldi Kim is a Ph.D. candidate in Computer Science and
Engineering at the University of Washington.  Prior to moving to
Seattle she earned her B.A. in Computer Science at Harvard University
and a M. Eng. in Embedded Systems Design from the University of Lugano
in Lugano, Switzerland.  Her research interests are in computer
architecture, particularly its boundaries: in the hardware/ software
interaction, as well as the architecture/circuit interaction.  As a
graduate student she was a member of the WaveScalar research group and
developed an architecture to enable reduced-cost chip designs.